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1 zarlink semiconductor inc. zarlink, zl and the zarlink semiconductor logo are trademarks of zarlink semiconductor inc. copyright 2003-4, zarlink semiconductor inc. all rights reserved. key features ? conforms to ebu specification for dvb-s and directv specification for dss ? on-chip digital filtering supports 1 - 45 msps symbol rates ? on-chip 60 or 90 mhz dual-adc ? high speed scanning mode for blind symbol rate/code rate acquisition ? automatic spectral inversion resolution ? high level software interface for minimum development time ? up to 22 mhz lnb frequency tracking ? diseqc? v2.2: receive/transmit for full control of lnb, dish and other components ? compact 64 pin lqfp package (7 x 7 mm) ? sleep pin gives ~1,000 fold reduction in power to help products meet energy star ? requirements applications ? dvb 1 - 45 msps compliant satellite receiver ? dss 20 msps compliant satellite receivers ? smatv trans-modulators. (single master antenna tv) ? satellite pc applications description the zl10312 is a qpsk/bpsk 1 - 45 msps demodulator and channel decoder for digital satellite television transmissions to the european broadcast union ets 300 421 specification. it receives analogue i and q signals from the tuner, digitises and digitally demodulates this signal, and implements the complete dvb/dss fec (forward error correction), and de- scrambling function. the output is in the form of mpeg2 or dss transport stream data packets. the zl10312 also provides automatic gain control to the rf front-end device. july 2004 ordering information zl10312qcg 64-pin lqfp ZL10312UBH die supplied in wafer form* * please contact sales for further details 0 c to +70 c zl10312 satellite channel decoder data sheet figure 1 - functional block diagram i i/p q i/p dual adc de-rotator decimation filtering timing recovery matched filter phase recovery mpeg/ dss packets bus i/o 2-wire bus interface acquisition control clock generation analog agc control dvb dss fec
zl10312 data sheet 2 zarlink semiconductor inc. the zl10312 has a serial 2-wire bus interface to the control microprocessor. minimal software is required to control the zl10312 because of the built in automatic search and decode control functions. figure 2 - zl10312 pin allocation note: all supply pins must be connected as they are not all commoned internally. pin table no. name no. name no. name no. name 1reset 17 cvdd 33 gnd 49 mdo[1] 2 diseqc[2] 18 gnd 34 cvdd 50 cvdd 3diseqc[1]19 xti 35 addr[1] 51 gnd 4 diseqc[0] 20 xto 36 addr[2] 52 mdo[2] 5 vdd 21 gnd 37 addr[3] 53 mdo[3] 6 gnd 22 cvdd 38 addr[4] 54 gnd 7 cvdd 23 gnd 39 vdd 55 vdd 8 gnd 24 iin 40 gnd 56 mdo[4] 9 sleep 25 iin 41 agc 57 mdo[5] 10 clk1 26 gnd 42 test 58 gnd 11 data1 27 vdd 43 irq 59 cvdd 12 cvdd 28 gnd 44 cvdd 60 mdo[6] 13 gnd 29 qin 45 gnd 61 mdo[7] 14 data2 30 qin 46 mostrt 62 moclk 15 clk2 31 gnd 47 moval 63 bkerr 16 oscmode 32 cvdd 48 mdo[0] 64 status
zl10312 data sheet table of contents 3 zarlink semiconductor inc. 1.0 functional overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 1.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 1.2 analogue-to-digital converter and pll. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 1.3 qpsk demodulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 1.4 forward error correction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 2.0 electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 2.1 recommended operating condition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 2.2 absolute maximum ratings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 2.3 primary 2-wire bus timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 2.4 crystal specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 2.5 electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 2.6 zl10312 pinout description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 2.7 alphabetical listing of pin-out . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
zl10312 data sheet 4 zarlink semiconductor inc. overview the zl10312 is a qpsk/bpsk 1 - 45 msps demodulator and channel decoder for digital satellite television transmissions compliant to both dvb-s and dss standards and other systems. a command driven control (cdc) system is provided making the zl10312 very simple to program. after the tuner has been programmed to the required frequency to acquire a dvb transmission, the zl10312 requires a minimum of five registers to be written. the zl10312 provides a monitor of bit error rate after the qpsk module and also after the viterbi module. for receiver installation, a high speed scan or 'blind search' mode is available. this allows all signals from a given satellite to be evaluated for frequency, symbol rate and convolutional coding scheme. the phase of the iq signals can be automatically determined. full diseqc?v2.x is provided for both writing and reading diseqc? messages. storage in registers for up to eight data bytes sent and eight data bytes received is provided. additional features ? 2-wire bus microprocessor interface with separate interface to tuner ? all digital clock and carrier recovery ? on-chip pll clock generation using low cost 10 to 16 mhz crystal ? low power operation, with stand-by and sleep modes ? 3.3 v operation with 1.8 v for core logic ? 7 x 7mm 64 pin lqfp package ? low external component count ? commercial temperature range 0 to 70c demodulator ? bpsk or qpsk programmable ? optional fast acquisition mode for low symbol rates viterbi ? programmable decoder rates 1/2, 2/3, 3/4, 5/6, 6/7, 7/8 ? automatic spectral inversion resolution ? constraint length k=7 ? trace back depth 128 ? extensive snr and ber monitors de-interleaver ? compliant with dvb and dss standards reed solomon ? (204, 188) for dvb and (146,130) for dss ? reed solomon bit-error-rate monitor to indicate viterbi performance de-scrambler ? ebu specification de-scrambler for dvb mode outputs ? mpeg transport parallel & serial output ? integrated mpeg2 tei bit processing for dvb only application support ? design manual ? channel decoder system evaluation board ? windows based evaluation software ? ansi-c generic software
zl10312 data sheet 5 zarlink semiconductor inc. figure 3 - typical application schematic
zl10312 data sheet 6 zarlink semiconductor inc. 1.0 functional overview 1.1 introduction zl10312 is a single-chip variable rate digital qpsk/bpsk satellite demodulator and channel decoder. the zl10312 accepts base-band in-phase and quadrature analogue signals and delivers an mpeg or dss packet data stream. digital filtering in zl10312 removes the need for programmable external anti-alias filtering for all symbol rates from 1 - 45 msps. frequency, timing and carrier phase recovery are all digital and the only feed-back to the analogue front-end is for automatic gain control. the digital phase recovery loop enables very fine bandwidth control that is needed to overcome performance degradation due to phase and thermal noise. all acquisition algorithms are built into the zl10312 controller. the zl10312 can be operated in a command driven control (cdc) mode by specifying the symbol rate and viterbi code rate. there is also a provision for a search for unknown symbol rates and viterbi code rates. 1.2 analogue-to-digital converter and pll the a/d converters sample single-ended or differential analogue inputs and consist of a dual adc and circuitry to provide improved sinad (signal-noise and distortion) and channel matching. the fixed rate sampling clock is provided on-chip using a programmable pll needing only a low cost 10 to 16 mhz crystal. different crystal frequencies can be combined with different pll ratios, depending on the maximum symbol rate, allowing a very flexible approach to clock generation. an external clock signal in the range 4 to 16 mhz can also be used as the master clock. 1.3 qpsk demodulator the demodulator in the zl10312 consists of signal amplitude offset compensation, frequency offset compensation, decimation filtering, carrier recovery, symbol recovery and matched filtering. the decimation filters give continuous operation from 2mbits/s to 90mbits/s allowing one receiver to cover the needs of the consumer market as well as the single carrier per channel (scpc) market with the same components without compromising performance, that is, the channel reception is within 0.5db of theoretical. for a given symbol rate, control algorithms on the chip detect the number of decimation stages needed and switch them in automatically. the frequency offset compensation circuitry is capable of tracking out up to 22.5 mhz frequency offset. this allows the system to cope with relatively large frequency uncertainties introduced by the low noise block (lnb). full control of the lnb is provided by the diseqc? outputs from the zl10312. horizontal/vertical polarisation and an instruction modulated 22khz signal are available under register control. all diseqc? v2.x functions are implemented on the zl10312. an internal state machine that handles all the demodulator functions controls the signal acquisition and tracking. various pre-set modes are available as well as blind acquisition where the receiver has no prior knowledge of the received signal. fast acquisition algorithms have been provided for low symbol rate applications. full interactive control of the acquisition function is possible for debug purposes. in the event of a signal fade or a cycle slip, the qpsk demodulator allows sufficient time for the fec to re-acquire lock, for example, via a phase rotation in the viterbi decoder. this is to minimise the loss of signal due to the signal fade. only if the fec fails to re-acquire lock for a long period (which is programmable) would qpsk try to re-acquire the signal. the matched filter is a root-raised-cosine filter with either 0.20 or 0.35 roll-off, compliant with dss and dvb standards. although not a part of the dvb standard, zl10312 allows a roll-off of 0.20 to be used with other dvb parameters. an agc signal is provided to control the signal levels in the tuner section of the receiver and ensure the signal level fed to the zl10312 is set at an optimal value under all reception conditions. the zl10312 provides comprehensive information on the input signal and the state of the various parts of the device. this information includes signal to noise ratio (snr), signal level, agc lock, timing and carrier lock signals. a maskable interrupt output is available to inform the host controller when events occur.
zl10312 data sheet 7 zarlink semiconductor inc. 1.4 forward error correction the zl10312 contains fec blocks to enable error correction for dvb-s and dss transmissions. the viterbi decoder block can decode the convolutional code with rates 1/2, 2/3, 3/4, 5/6, 6/7 or 7/8. the block features automatic synchronisation, automatic spectral inversion resolution and automatic code rate detection. the trace back depth of 128 provides better performance at high code rates and the built-in synchronisation algorithm allows the viterbi decoder to lock onto signals with very poor signal-to-noise ratios. a viterbi bit error rate monitor provides an indication of the error rate at the qpsk output. the 24-bit error count register in the viterbi decoder allows the bit error rate at the output of the qpsk demodulator to be monitored. the 24-bit bit error count register in the reed-solomon decoder allows the viterbi output bit error rate to be monitored. the 16-bit uncorrectable packet counter yields information about the output packet error rate. these three monitors and the qpsk snr register allow the performance of the device and its individual components, such as the qpsk demodulator and the viterbi decoder, to be monitored extensively by the external microprocessor. the frame/byte align block features a sophisticated synchronisation algorithm to ensure reliable recovery of dvb and dss framed data streams under worst case signal conditions. the de-interleaver uses on-chip ram and is compatible with the dvb and dss algorithms. the reed-solomon decoder is a truncated version of the (255, 239) code. the code block size is 204 for dvb and 146 for dss. the decoder provides a count of the number of uncorrectable blocks as well as the number of bit errors corrected. the latter gives an indication of the bit error rate at the output of the viterbi decoder. in dvb mode, spectrum de-scrambling is performed compatible with the dvb specification. the final output is a parallel or serial transport data stream; packet sync; data clock; and a block error signal. the data clock may be inverted under software control. 2.0 electrical characteristics 2.1 recommended operating condition parameter symbol min. typ. max. units core power supply voltage cvdd 1.71 1.8 1.89 v periphery power supply voltage vdd 3.13 3.3 3.47 v input clock frequency (note 1 ) 1. when not using a crystal, xti may be driven from an external source over the frequency range shown. fxt1 3.99 16.01 mhz crystal oscillator frequency fxt2 9.99 16.01 mhz clk1 clock frequency 2 (with 10 mhz or above) 2. the maximum serial clock speed on the primary 2-wire bus is related to the input clock frequency and is limited to 100khz wi th a 4.0 mhz clock. fclk1 400 khz ambient operating temperature 0 70 c
zl10312 data sheet 8 zarlink semiconductor inc. 2.2 absolute maximum ratings note 1: stresses exceeding these listed under 'absolute ratings' may induce failure. exposure to absolute maximum ratings for extended periods may reduce reliability. functionality at or above these conditions is not implied. 2.3 primary 2-wire bus timing figure 4 - primary 2-wire bus timing where: s = start sr = restart, i.e. start without stopping first. p = stop. maximum operating conditions parameter symbol min. max. unit power supply vdd -0.3 +4.5 v power supply cvdd -0.3 2.3 v voltage on input pins (5v rated) vi -0.3 5.5 v voltage on input pins (3.3v rated) vi -0.3 vdd + 0.3 v voltage on input pins (1.8v rated, i.e. xti ) vi -0.3 cvdd + 0.3 v voltage on output pins (5v rated) vo -0.3 6.5 v voltage on output pins (3.3v rated) vo -0.3 vdd + 0.3 v voltage on output pins (1.8v rated, i.e. xto) vo -0.3 cvdd + 0.3 v storage temperature tstg -55 150 c operating ambient temperature top 0 70 c junction temperature tj 125 c esd protection (human body model) 4 kv
zl10312 data sheet 9 zarlink semiconductor inc. 2.4 crystal specification parallel resonant fundamental frequency (preferred) 9.99 to 16.00 mhz. tolerance over operating temperature range 25 ppm. tolerance overall 50 ppm. nominal load capacitance 30 pf. equivalent series resistance <35 ? figure 5 - crystal oscillator circuit note: the crystal frequency should be chosen to ensure that the system clock would marginally exceed the maximum symbol rate required, e.g. 10.111 mhz with a multiplier of x9 will give a 91 mhz system clock to guarantee 45 msps operation. parameter: primary 2-wire bus only symbol value unit min. max. clk1 clock frequency (for xti 10 mhz) fclk 0 400 khz bus free time between a stop and start condition. to 1300 ns hold time (repeated) start condition. thd;sta 600 ns low period of clk1 clock. tlow 1300 ns high period of clk1 clock. thigh 600 ns set-up time for a repeated start condition. tsu;sta 600 ns data hold time (when input). thd;dat 0 ns data set-up time tsu;dat 100 ns rise time of both clk1 and data1 signals. tr 20+0.1cb 1 note 2 ns fall time of both clk1 and data1 signals, (100pf to ground) tf 20+0.1cb 1 300 ns set-up time for a stop condition. tsu;sto 600 ns table 1 - primary 2-wire bus timing 1. cb = the total capacitance on either clock or data line in pf. 2. the rise time depends on the external bus pull up resistor and bus capacitance.
zl10312 data sheet 10 zarlink semiconductor inc. 2.5 electrical characteristics dc electrical characteristics parameter conditions/pin symbol min. typ. max. unit core voltage cvdd 1.71 1.8 1.89 v peripheral voltage vdd 3.13 3.3 3.47 v core current 45 msps cr 7/8 91 mhz system clock cidd 160 216 ma peripheral current idd 10 11.25 ma to ta l p o we r (91 mhz system clock) ptot1 320 450 mw to ta l p o we r (stand-by) ptot2 2.2 3.3 mw total power (sleep) pin 9 = logic ?1? adcs powered down ptot3 0.35 0.525 mw output low level 2, 6 or 12 ma per output (see section 2.6, zl10312 pinout description) vol 0.4 v output high level 2, 6 or 12 ma per output voh 2.4 v output leakage tri-state when off or open-drain when high 1 a output capacitance all outputs except xto, clk1 & open-drain types. excludes packaging contribution (~0.35 pf) 2.7 pf open-drain outputs. excludes packaging contribution (~0.35 pf) 3.3 pf input low level vil 0.8 v input high level vih 2.0 v input leakage vin = 0 or vdd 1 a input capacitance excludes packaging contribution (~0.35pf) 1.5 pf ac electrical characteristics parameter conditions/pin min. typ. max. unit adc full-scale input single range (single-ended or differential) differential source is recommended 0.5 1.0 vpp adc analog input resistance per input pin 10 k ? adc input common mode voltage level 0.7 1.7 v
zl10312 data sheet 11 zarlink semiconductor inc. 2.6 zl10312 pinout description pin description table pin name description i/o note v ma 1 reset active low reset input i cmos 1 5 2 diseqc[2] diseqc? input for level 2 control. also usable as gpp2 (general purpose port pin) for other purposes. i/o open drain 1 56 3 diseqc[1] horizontal/vertical lnb control (acts as input only in production test modes) i/o cmos 3.3 2 4 diseqc[0] 22 khz output to lnb (acts as input only in production test modes) i/o cmos 3.3 2 9 sleep stops oscillator and sets minimum power levels to entire device (except adcs - register controlled power-down) icmos 3.3 10 clk1 primary 2-wire serial bus clock i cmos 1 5 11 data1 primary 2-wire serial bus data i/o open drain 1 56 14 data2 secondary 2-wire bus data to tuner front end. also usable as gpp1 (general purpose port pin) for other purposes. i/o open drain 1 56 15 clk2 secondary 2-wire bus clock to tuner front end. also usable as gpp0 (general purpose port pin) for other purposes. i/o open drain 1 56 16 oscmode controls oscillator mode to suit crystal or external signal i cmos 3.3 19 xti crystal input or external reference clock input i cmos 1.8 20 xto crystal output, includes internal feedback resistor to xti i/o cmos 1.8 24 iin i channel input i analog 25 iin i channel negative input i analog 29 qin q channel negative input i analog 30 qin q channel input i analog 35,36,37 38 addr[1:4] primary 2-wire bus address defining pins i cmos 3.3 41 agc agc sigma-delta output (acts as input only in production test modes) i/o open drain 1 56 42 test for normal operation, this pin must be held at 0v. i cmos 3.3 43 irq active low interrupt output. reading all active interrupt registers resets this pin (acts as input only in production test modes) i/o open drain 1 56 46 mostrt mpeg output start signal. high during the first byte of a packet. ocmos tri-state 3.3 2
zl10312 data sheet 12 zarlink semiconductor inc. note 1: 5 v tolerant pins with thresholds related to 3.3 v. 47 moval mpeg data output valid. high during the moclk cycles when valid data bytes are being output. ocmos tri-state 3.3 2 48,49,52, 53,56, 57,60,61 mdo[0:7] mpeg transport packet data output bus. can be tri-stated under control of a register bit. ocmos tri-state 3.3 2 62 moclk mpeg clock output at the data byte rate. o cmos tri-state 3.3 12 63 bkerr active low uncorrectable block indicator or no-signal indicator. mode selected by err_ind bit (#7) of the qpsk_diag_ctl register (add. 0x67). can also be inverted. ocmos tri-state 3.3 2 64 status status output. register defined function including audio frequency proportional to ber (acts as input only in production test modes) i/o cmos 3.3 2 5, 39, 55 vdd peripheral supply pins. all pins must be connected. 3.3 27 vdd peripheral supply pin used for the adc. 3.3 7, 12, 44, 50, 59 cvdd core supply pins. all pins must be connected. 1.8 17, 22, 32, 34 cvdd pll/adc supply pins. all pins must be connected. 1.8 6, 8, 13, 40, 45 51, 54, 58 gnd ground supply pins. all pins must be connected. 0 18, 21, 23 26, 28, 31, 33 gnd pll/adc ground supply pins. all pins must be connected. 0 pin description table (continued) pin name description i/o note v ma
zl10312 data sheet 13 zarlink semiconductor inc. 2.7 alphabetical listing of pin-out alphabetical listing of pin-out name no. name no. name no. name no. addr[1] 35 cvdd 59 gnd 40 moclk 62 addr[2] 36 data1 11 gnd 45 mostrt 46 addr[3] 37 data2 14 gnd 51 moval 47 addr[4] 38 diseqc[0] 4 gnd 54 oscmode 16 agc 41 diseqc[1] 3 gnd 58 qin 29 bkerr 63 diseqc[2] 2 iin 24 qin 30 clk1 10 gnd 6 iin 25 reset 1 clk2 15 gnd 8 irq 43 sleep 9 cvdd 7 gnd 13 mdo[0] 48 status 64 cvdd 12 gnd 18 mdo[1] 49 test 42 cvdd 17 gnd 21 mdo[2] 52 vdd 5 cvdd 22 gnd 23 mdo[3] 53 vdd 27 cvdd 32 gnd 26 mdo[4] 56 vdd 39 cvdd 34 gnd 28 mdo[5] 57 vdd 55 cvdd 44 gnd 31 mdo[6] 60 xti 19 cvdd 50 gnd 33 mdo[7] 61 xto 20

www.zarlink.com information relating to products and services furnished herein by zarlink semiconductor inc. or its subsidiaries (collectively ?zarlink?) is believed to be reliable. however, zarlink assumes no liability for errors that may appear in this publication, or for liability otherwise arising from t he application or use of any such information, product or service or for any infringement of patents or other intellectual property rights owned by third parties which may result from such application or use. neither the supply of such information or purchase of product or service conveys any license, either express or implied, u nder patents or other intellectual property rights owned by zarlink or licensed from third parties by zarlink, whatsoever. purchasers of products are also hereby notified that the use of product in certain ways or in combination with zarlink, or non-zarlink furnished goods or services may infringe patents or other intellect ual property rights owned by zarlink. this publication is issued to provide information only and (unless agreed by zarlink in writing) may not be used, applied or re produced for any purpose nor form part of any order or contract nor to be regarded as a representation relating to the products or services concerned. the products, t heir specifications, services and other information appearing in this publication are subject to change by zarlink without notice. no warranty or guarantee express or implied is made regarding the capability, performance or suitability of any product or service. information concerning possible methods of use is provided as a guide only and does not constitute any guarantee that such methods of use will be satisfactory in a specific piece of equipment. it is the user?s responsibility t o fully determine the performance and suitability of any equipment using such information and to ensure that any publication or data used is up to date and has not b een superseded. manufacturing does not necessarily include testing of all functions or parameters. these products are not suitable for use in any medical products whose failure to perform may result in significant injury or death to the user. all products and materials are sold and services provided subject to zarlink?s conditi ons of sale which are available on request. purchase of zarlink?s i 2 c components conveys a licence under the philips i 2 c patent rights to use these components in and i 2 c system, provided that the system conforms to the i 2 c standard specification as defined by philips. zarlink, zl and the zarlink semiconductor logo are trademarks of zarlink semiconductor inc. copyright zarlink semiconductor inc. all rights reserved. technical documentation - not for resale for more information about all zarlink products visit our web site at

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